Polyphase clock generation circuit

ABSTRACT

A single-phase clock and an output signal of a second delay circuit are inputted to a first NAND gate and a first NOR gate. The output signal of the first NAND gate is inputted to a gate of a first PMOS transistor of a first clock driver. The output signal of the first NOR gate is inputted to a gate of a first NMOS transistor of the first clock driver. Meanwhile, an inverted clock outputted from an inverter and an output signal of a first delay circuit are inputted to a second NAND circuit and a second NOR circuit. The output signal of the second NAND gate is inputted to a gate of a second PMOS transistor of a second clock driver. The output signal of the second NOR gate is inputted to a gate of a second NMOS transistor of the second clock driver.

BACKGROUND OF THE INVENTION

The present invention relates to a polyphase clock generation circuitwhich employs a clock driver of the Complementary Metal OxideSemiconductor (CMOS) inverter configuration.

In recent years, there has been a progressively increasing demand forhigh-speed operation and low-power dissipation in semiconductorintegrated circuits for use in microcomputers or like electronicapparatus in which desired processing is executed in response topolyphase clocks. However, the characteristics of actual semiconductorintegrated circuits cannot satisfy this demand because the powerdissipation of these circuits increases as the speed of operationincreases. As a conventional example of polyphase clock generationcircuit used to generate polyphase clocks in such semiconductorintegrated circuits, a two-phase clock generation circuit whichgenerates from a single-phase clock φ a first clock φ₁ and a secondclock φ₂ of different phase is described below with reference to FIG. 1.

The two-phase clock generation circuit 100 includes an inverter 101, afirst NAND gate 102, a second NAND gate 103, a first delay circuit 104,a second delay circuit 105, a first clock driver 106, and a second clockdriver 107. The inverter 101 inverts the polarity of the single-phaseclock φ to produce an inverted clock φ'. The first NAND gate 102 negatesthe logical AND between the single-phase clock φ and the output signalof the second delay circuit 105. The second NAND gate 103 negates thelogical AND between the inverted clock φ' and the output signal of thefirst delay circuit 104. The first delay circuit 104 delays the outputsignal of the first NAND gate 102 by a predetermined first delay timedt₁. The second delay circuit 105 delays the output signal of the secondNAND gate 103 by a predetermined second delay time dt₂. The first clockdriver 106 has the configuration of a CMOS inverter formed from a firstPMOS transistor M_(p1) and a first NMOS transistor M_(n1), and invertsthe polarity of the output signal of the first NAND gate 102 to producethe first clock φ₁. The second driver 107 has the configuration of aCMOS inverter formed from a second PMOS transistor M_(p2) and a secondNMOS transistor M_(n2), and inverts the polarity of the output signal ofthe second NAND gate 103 to produce the second clock φ₂.

The operation of the two-phase clock generation circuit 100 is describedwith reference to a timing chart shown in FIG. 2. It is assumed that, asan initial state, sufficient time has passed while the single-phaseclock φ remains at high level and the two-phase clock generation circuit100 is in a stable condition. In this condition, the first clock φ₁ isat high level while the second clock φ₂ is at low level, as shown attime t₀ in FIG. 2. When the single-phase clock φ subsequently changes tolow level at time t₁, the output signal of the first NAND gate 102changes to high level, and consequently, the first clock φ₁ changes fromhigh level to low level after the delay of the delay time provided bythe first clock driver 106. Meanwhile, at time t₁, the inverted clock φ'outputted from the inverter 101 changes to high level. However, sincethe output signal of the first NAND gate 102 is inputted to the secondNAND gate 103 only after the delay of the delay time dt₁ of the firstdelay circuit 104, the output signal of the first NAND gate 102 changesfrom high level to low level after the delay of the first delay time dt₁from time t₁. As the delay time at the second clock driver 107 issubstantially equal to the delay time at the first clock driver 106, thesecond clock φ₂ changes from low level to high level after the delay ofthe first delay time dt₁ that commences when the first clock φ₁ changesfrom high level to low level. Thereafter, when the single-phase clock φchanges from low level to high level at time t₂, the inverted clock φ'outputted from the inverter 101 changes to low level. As a result, theoutput signal of the second NAND gate 103 changes to high level and thesecond clock φ₂ changes from high level to low level after the delay ofthe delay time at the second clock driver 107. Meanwhile, at time t₂,the output signal of the second NAND gate 103 changes to high level.However, since the output signal of the second NAND gate 103 is inputtedto the first NAND gate 102 after the delay of the second delay time dt₂of the second delay circuit 105, the output signal of the first NANDgate 102 changes from high level to low level after the delay of thesecond delay time dt₂ from the time t₂. As the delay time at the firstclock driver 106 is substantially equal to the delay time at the secondclock driver 107, the first clock φ₁ changes from low level to highlevel after the delay of the second delay time dt₂ that commences whenthe second clock φ₂ changes from high level to low level. Thereafter,the operations described above take place repetitively. Accordingly, inthe two-phase clock generation circuit 100, the first and second clocksφ₁ and φ₂ do not exhibit an overlapping condition of high level thereofand repeat their level variations in synchronism with the single-phaseclock φ.

In a semiconductor integrated circuit in which processing is executed inresponse to polyphase clocks, it is normally necessary that activeperiods (periods of high level or low level) of the clocks do notoverlap with each other. This is because cases in which the activeperiods of the clocks overlap with each other can cause malfunction ofthe semiconductor integrated circuit such as a direct transmissionphenomenon of data in a latch of the master-slave configuration.Accordingly, a polyphase clock generation circuit must generate clockssuch that the magnitude of the displacement between the timing of alevel variation of one clock and the timing of a level variation ofanother clock (that is, a delay between the clocks) may be greater thanthe magnitude of the gradient of the waveform of the rising or fallingedge of the one clock. However, the magnitude of the gradient of thewaveform of the rising or falling edge of the clock depends upon thepower source voltage for driving the polyphase clock generation circuit(that is, an application of the polyphase clock generation circuit), theweight of the lead to the polyphase clock generation circuit, andvarious other parameters. For example, the gradient of the waveform ofthe rising or falling edge of the clock when the polyphase clockgeneration circuit is used with a system wherein the power sourcevoltage is 3 V is higher than that when the polyphase clock generationcircuit is used with another system wherein the power source voltage is5 V, and accordingly, the delay between the clocks must be greater wherethe power source voltage is 3 V. However, although increasing the delaybetween clocks increases the margin of safety against malfunctions,increased delay also decreases the operation speed of the semiconductorintegrated circuit which operates with the clocks. Accordingly, as thedelay between clocks has an appropriate magnitude suitable for theapplication, a polyphase clock generation circuit is preferablyconstructed so as to allow adjustment of the delay between clocks fromthe outside in order to increase the applicability of the polyphaseclock generation circuit to various applications.

Since the first clock driver 106 shown in FIG. 1 is constructed from theinverter of the CMOS configuration formed from the first PMOS transistorM_(p1) and the first NMOS transistor M_(n1), it has input/outputcharacteristic such as the characteristics illustrated in FIG. 3. Whenthe input voltage V_(IN) to the first clock driver 106 (that is, thevoltage of the output signal of the first NAND gate 102) issubstantially equal to 0 V, the first PMOS transistor M_(p1) is ON andthe first NMOS transistor M_(n1) is OFF, and consequently, the outputvoltage V_(OUT) of the first clock driver 106 (that is, the voltage ofthe first clock φ₁) is substantially equal to the power source voltageV_(DD). On the other hand, when the input voltage V_(IN) issubstantially equal to the power source voltage V_(DD), the first PMOStransistor M_(p1) is OFF and the first NMOS transistor M_(n1) is ON, andconsequently, the output voltage V_(OUT) is substantially equal to 0 V.Accordingly, within a period within which the first clock driver 106 isin a stable condition, such as a period "a" or another period "c" shownin FIG. 3, at least one of the first PMOS transistor M_(p1) and thefirst NMOS transistor M_(n1) is OFF, and no through-current flowsthrough the first clock driver 106. As a result, the power dissipationof the first clock driver 106 in a stable condition is very low.However, within a period of a transition condition such as a period "b"shown in FIG. 3, the first PMOS transistor M_(p1) and the first NMOStransistor M_(n1) are both ON, and through-current flows through thefirst clock driver 106. The through-current increases as the channelwidths (that is, the conductance) of the first PMOS transistor M_(p1)and the first NMOS transistor M_(n1) increase and as the operationfrequency (that is, the frequency of the single-phase clock φ)increases.

Accordingly, conventional polyphase clock generation circuits whichinclude clock drivers of the CMOS inverter configuration such as thetwo-phase clock generation circuit 100 shown in FIG. 1 have problems inthat the power dissipation is high since through-current flows uponswitching of the clock drivers, that the power dissipation by the clockdrivers increases as the operation frequency increases, and that powersource noise or ground noise is produced.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a polyphase clockgeneration circuit which can achieve reduction of the power dissipationand prevention of production of power source noise and ground noise bysuppressing production of through-current upon switching of clockdrivers of the CMOS inverter configuration using a delay between clocks.

Other objects of the present invention will become obvious from thefollowing description.

In accordance with an aspect of the present invention, there is provideda polyphase clock generation circuit which comprises: a first powersource voltage terminal; a second power source voltage terminal; a clockdriver including a P-channel field-effect transistor with a sourceconnected to the first power source voltage terminal, and an N-channelfield-effect transistor with a source connected to the second powersource voltage terminal and a drain connected to a drain of theP-channel field-effect transistor; and clock driver driving means forturning on the P-channel field-effect transistor and the N-channelfield-effect transistor alternately and independently of each other sothat the P-channel field-effect transistor and N-channel field-effecttransistor may not have an ON-state simultaneously with each other.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and advantages of the present invention will becomeapparent from the following description when taken in conjunction withthe accompanying drawings in which:

FIG. 1 is a circuit diagram showing a two-phase clock generation circuitwhich is a conventional example of a polyphase clock generation circuit;

FIG. 2 is a timing chart illustrating operation of the two-phase clockgeneration circuit shown in FIG. 1;

FIG. 3 is a graph illustrating the input/output characteristic of thefirst clock driver shown in FIG. 1;

FIG. 4 is a circuit diagram of a two-phase clock generation circuitaccording to a first embodiment of a polyphase clock generation circuitof the present invention;

FIG. 5 is a timing chart illustrating operation of the two-phase clockgeneration circuit shown in FIG. 4;

FIG. 6 is a circuit diagram of a two-phase clock generation circuitaccording to a second embodiment of a polyphase clock generation circuitof the present invention;

FIG. 7 is a timing chart illustrating operation of the two-phase clockgeneration circuit shown in FIG. 6;

FIG. 8 is a circuit diagram of a four-phase clock generation circuitaccording to a third embodiment of a polyphase clock generation circuitof the present invention;

FIG. 9 is a timing chart illustrating operation of the two-phase clockgeneration circuit shown in FIG. 8;

FIG. 10 is a circuit diagram of a two-phase clock generation circuitaccording to a fourth embodiment of a polyphase clock generation circuitof the present invention;

FIG. 11 is a timing chart illustrating operation of the two-phase clockgeneration circuit shown in FIG. 10 when the voltage is low; and

FIG. 12 is a timing chart illustrating operation of the two-phase clockgeneration circuit shown in FIG. 10 when the voltage is high.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A two-phase clock generation circuit 10 according to the firstembodiment of a polyphase clock generation circuit of the presentinvention includes, as shown in FIG. 4, an inverter 11, a first NANDgate 12, a first NOR gate 13, a second NAND gate 14, a second NOR gate15, a first delay circuit 16, a second delay circuit 17, a first clockdriver 18, and a second clock driver 19. The inverter 11 inverts thepolarity of a single-phase clock φ to produce an inverted clock φ'. Thefirst NAND gate 12 negates the logical AND between the single-phaseclock φ and the output signal of the second delay circuit 17. The firstNOR gate 13 negates the logical OR between the single-phase clock φ andthe output signal of the second delay circuit 17. The second NAND gate14 negates the logical AND between the inverted clock φ' and the outputsignal of the first delay circuit 16. The second NOR gate 15 negates thelogical OR between the inverted clock φ' and the output signal of thefirst delay circuit 16. The first delay circuit 16 delays the outputsignal of the first NOR gate 13 by a predetermined first delay time dt₁.The second delay circuit 17 delays the output signal of the second NORgate 15 by a predetermined second delay time dt₂. The first clock driver18 has the configuration of the CMOS inverter formed from a first PMOStransistor M_(p1) with a gate to which the output signal of the firstNAND gate 12 is inputted and a first NMOS transistor M_(n1) with a gateto which the output signal of the first NOR gate 13 is inputted. Thefirst clock driver produces a first clock φ₁ from the output signal ofthe first NAND gate 12 and the output signal of the first NOR gate 13.The second clock driver 19 has the configuration of a CMOS inverterformed from a second PMOS transistor M_(p2) with a gate to which theoutput signal of the second NAND gate 14 is inputted and a second NMOStransistor M_(n2) with a gate to which the output signal of the secondNOR gate 15 is inputted. The second clock driver produces a second clockφ₂ from the output signal of the second NAND gate 14 and the outputsignal of the second NOR gate 15. The source of the first PMOStransistor M_(p1) and the source of the second PMOS transistor M_(p2)are both connected to a power source voltage terminal 20. The source ofthe first NMOS transistor M_(n1) and the source of the second NMOStransistor M_(n2) are both grounded. The drain of the first PMOStransistor M_(p1) and the drain of the first NMOS transistor M_(n1) areconnected to each other. The drain of the second PMOS transistor M_(p2)and the drain of the second NMOS transistor M_(n2) are connected to eachother.

The operation of the two-phase clock generation circuit 10 is describedwith reference to the timing chart of FIG. 5. It is assumed that, as aninitial stage, sufficient time has passed while the single-phase clock φis at high level and the two-phase clock generation circuit 10 is in astable condition. In this condition, the first clock φ₁ is at high leveland the second clock φ₂ is at low level, as shown at time t₀ in FIG. 5.The two input signals to the first NOR gate 13 (that is, thesingle-phase clock φ and the output signal of the second delay circuit17) both exhibit high level for a period of time from time t₀ to timet₁, where t₁ represents the time at which the single-phase clock φchanges from high level to low level. Consequently, the output signal ofthe first NOR gate 13 is at low level, and the first NMOS transistorM_(n1) is OFF. At this point in time, since the two input signals to thesecond NAND gate 14 (that is, the inverted clock φ' and the outputsignal of the first delay circuit 16) are both at low level, the outputsignal of the second NAND gate 14 exhibits high level, and the secondPMOS transistor M_(p2) is consequently OFF. Thereafter, when thesingle-phase clock φ changes to low level at time t₁, the output signalof the first NAND gate 12 changes to high level, and the first PMOStransistor M_(p1) is consequently turned OFF. At this point in time,since the inverted clock φ' outputted from the inverter 11 is at highlevel, the output signal of the second NOR gate 15 changes to low level,and the second NMOS transistor M_(n2) is consequently turned OFF. Sincethe output signal of the second NOR gate 15 is inputted to the first NORgate 13 by way of the second delay circuit 17, the output signal of thefirst NOR gate 13 changes from low level to high level after the delayof the second delay time dt₂ that commences when the output signal ofthe second NOR gate 15 changes to low level at time t₁. As a result, thefirst NMOS transistor M_(n1) is turned ON, and the first clock φ₁changes from high level to low level. Since the output signal of thefirst NOR gate 13 is inputted to the second NAND gate 14 by way of thefirst delay circuit 16, the output signal of the second NAND gate 14changes from high level to low level after the delay of the first delaytime dt₁ that commences when the output signal of the first NOR gate 13changes to low level. As a result, the second PMOS transistor M_(p2) isturned ON, and the second clock φ₂ changes from low level to high level.In this manner, in the two-phase clock generation circuit 10, the firstPMOS transistor M_(p1) constituting the first clock driver 18 and thesecond NMOS transistor M_(n2) constituting the second clock driver 19are turned OFF in synchronism with the falling edge of the single-phaseclock φ, and the first NMOS transistor M_(n1) is turned ON after thedelay substantially of the second delay time dt₂ from the falling edgeof the single-phase clock φ, and the second PMOS transistor M_(p2) isthen turned ON after the delay of a delay time approximately equal tothe sum dt₁ +dt₂ of the first delay time dt₁ and the second delay timedt₂ from the falling edge of the single-phase clock φ. Accordingly,before the first clock φ₁ changes from high level to low level, aperiod, shown by a period "Hi" in FIG. 5, within which the outputimpedance of the first clock driver 18 exhibits high level (that is, theperiod within which the first PMOS transistor M_(p1) and the first NMOStransistor M_(n1) both exhibit an OFF state) appears. Before the secondclock φ₂ changes from low level to high level, a period, shown by aperiod "Hi" in FIG. 5, within which the output impedance of the secondclock driver 19 exhibits high level (that is, the period within whichthe second PMOS transistor M_(p2) and the second NMOS transistor M_(n2)both exhibit an OFF state) appears.

Thereafter, until the single-phase clock φ changes to high level at timet₂, the two input signals to the NAND gate 12 (that is, the single-phaseclock φ and the output signal of the second delay circuit 17) are bothat low level, whereby the output signal of the first NAND gate 12exhibits high level, and the first PMOS transistor M_(p1) is OFF.Meanwhile, since the two input signals to the second NOR gate 15 (thatis, the inverted clock φ' and the output signal of the first delaycircuit 16) are both at high level, the output signal of the second NORgate 15 presents low level, and the second NMOS transistor M_(p2) istherefore OFF. Thereafter, when the single-phase clock φ changes fromlow level to high level at time t₂, the output signal of the first NORgate 13 changes to low level, whereby the first NMOS transistor M_(n1)is turned OFF. At this point in time, the inverted clock φ' outputtedfrom the inverter 11 changes to low level, whereby the output signal ofthe second NAND gate 14 changes to high level and the second PMOStransistor M_(p2) is turned OFF. Since the output signal of the firstNOR gate 13 is inputted to the second NOR gate 15 by way of the firstdelay circuit 16, the output signal of the second NOR gate 15 changesfrom low level to high level after the delay of the first delay time dt₁that commences when the output signal of the first NOR gate 13 changesto low level. As a result, the second NMOS transistor M_(n2) is turnedON, and the second clock φ₂ changes from high level to low level.Meanwhile, since the output signal of the second NOR gate 15 is inputtedto the first NAND gate 12 by way of the second delay circuit 17, theoutput signal of the first NAND gate 12 changes from high level to lowlevel after the delay of the second delay time dt₂ that commences whenthe output signal of the second NOR gate 15 changes to high level. As aresult, the first PMOS transistor M_(p1) is turned ON, and the firstclock φ₁ changes from low level to high level. In this manner, in thetwo-phase clock generation circuit 10, the first NMOS transistor M_(n1)and the second PMOS transistor M_(p2) are turned OFF in synchronism withthe rising edge of the single-phase clock φ , and after the delaysubstantially of the first delay time dt₁ from the rising edge of thesingle clock φ, the second NMOS transistor M_(p2) is turned ON,following which the first PMOS transistor M_(p1) is turned ON after adelay time approximately equal to the sum dt₁ +dt₂ of the first delaytime dt₁ and the second delay time dt₂ from the rising edge of thesingle-phase clock φ. Accordingly, before the first clock φ₁ changesfrom low level to high level, a period, shown by a period "Hi" in FIG.5, within which the output impedance of the first clock driver 18exhibits high level (that is, the period within which the first PMOStransistor M_(p1) and the first NMOS transistor M_(n1) are both OFF)appears. Before the second clock φ₂ changes from high level to lowlevel, a period, shown by another period "Hi", in FIG. 5, within whichthe output impedance of the second clock driver 19 exhibits high level(that is, the period within which the second PMOS transistor M_(p2) andthe second NMOS transistor M_(n2) are both OFF) appears. Thereafter,operations similar to those from time t₁ to time t₂ described above takeplace repetitively. Accordingly, in the two-phase clock generationcircuit 10, the first clock φ₁ and the second clock φ₂ do not present anoverlapping condition of high level and repeat their level variations insynchronism with the single-phase clock φ. In other words, the firstclock φ₁ and the second clock φ₂ make two-phase clocks of active highlevel.

As is apparent from the foregoing description of the operation, with thetwo-phase clock generation circuit 10, periods within which the outputimpedance of the first clock driver 18 exhibit high level can beproduced after the rising edge and after the falling edge of thesingle-phase clock φ by individually and independently controlling atdifferent times the ON/OFF states of the first PMOS transistor M_(p1)and the first NMOS transistor M_(n1) that constitute the first clockdriver 18, and other periods within which the output impedance of thesecond clock driver 19 exhibit high level can be produced after therising edge and after the falling edge of the single-phase clock φ byindividually and independently controlling at different timings theON/OFF states of the second PMOS transistor M_(p2) and the second NMOStransistor M_(n2) that constitute the second clock driver 19.Consequently, through-current which is otherwise produced upon switchingof the first clock driver 18 and the second clock driver 19 can beeliminated. As a result, even if the frequency of the single-phase clockφ is increased, an increase of the through-current which increases inproportion to the increase of the frequency does not occur, andreduction in power dissipation can be achieved. Since a MOS transistorhaving a channel width of approximately 400 μm and having a very highcurrent supplying capacity is normally used for a system clock driver,for example, for a microcomputer, a through-current with a peak value of15 to 20 mA flows in conventional polyphase clock generation circuits.In contrast, very little through-current flows in the polyphase clockgeneration circuit 10. Consequently, the two-phase clock generationcircuit 10 allows construction of a system which has low powerdissipation, which produces little power source noise or ground noisedue to through-current, and which consequently provides highly reliableoperation.

A two-phase clock generation circuit 30 according to the secondembodiment of a polyphase clock generation circuit of the presentinvention is different from the two-phase clock generation circuit 10shown in FIG. 4 in that, as shown in FIG. 6, an output signal of a firstNAND gate 32 is inputted to a first delay circuit 36 and an outputsignal of a second NAND gate 34 is inputted to a second delay circuit37. The operation of the two-phase clock generation circuit 30 shown inFIG. 6 is described with reference to the timing chart shown in FIG. 7.It is assumed that, as an initial state, sufficient time has passedwhile the single-phase clock φ is at high level and the two-phase clockgeneration circuit 30 is in a stable condition. In this condition, thefirst clock φ₁ exhibits high level and the second clock φ₂ exhibits lowlevel as shown at time t₀ of FIG. 7.

The two input signals to the first NOR gate 33 (that is, thesingle-phase clock φ and the output signal of the second delay circuit37) both exhibit high level for a period of time from time t₀ to timet₁, where the time at which the single-phase clock φ changes from highlevel to low level is represented by t₁. Consequently, the output signalof the first NOR gate 33 is at low level, and the first NMOS transistorM_(n1) constituting the first clock driver 38 is OFF. At this point oftime, since the two input signals to the second NAND gate 34 (that is,the inverted clock φ' and the output signal of the first delay circuit36) are both at low level, the output signal of the second NAND gate 34exhibits high level and the second PMOS transistor M_(p2) constitutingthe second clock driver 39 is OFF. Thereafter, when the single-phaseclock φ changes to low level at time t₁, the output signal of the firstNAND gate 32 changes to high level and the first PMOS transistor M_(p1)constituting the first clock driver 38 is turned OFF. At this point oftime, since the inverted clock φ' outputted from the inverter 31 changesto high level, the output signal of the second NOR gate 35 changes tolow level, and the second NMOS transistor M_(n2) constituting the secondclock driver 39 is turned OFF. Since the output signal of the first NANDgate 32 is inputted to the second NOR gate 34 by way of the first delaycircuit 36, the output signal of the second NAND gate 34 changes fromhigh level to low level after the first delay time dt₁ that commenceswhen the output signal of the first NAND gate 32 changes to low level.As a result, the second PMOS transistor M_(p2) is turned ON, and thesecond clock φ₂ changes from low level to high level. Further, since theoutput signal of the second NAND gate 34 is inputted to the first NORgate 33 by way of the second delay circuit 37, the output signal of thefirst NOR gate 33 changes from low level to high level after the delayof the second delay time dt₂ that commences when the output signal ofthe second NAND gate 34 changes to low level at time t₁ +dt₁. As aresult, the first NMOS transistor M_(n1) is turned ON, and the firstclock φ₁ changes from high level to low level. In this manner, in thetwo-phase clock generation circuit 30, the first PMOS transistor M_(p1)and the second NMOS transistor M_(n2) are turned OFF in synchronism withthe falling edge of the single-phase clock φ, and the second PMOStransistor M_(p2) is turned ON after a delay approximately equal to thefirst delay time dt₁ from the falling edge of the single-phase clock φ,following which the first NMOS transistor M_(n1) is turned ON after thedelay time approximately equal to the sum dt₁ +dt₂ of the first delaytime dt₁ and the second delay time dt₂ from the falling edge of thesingle-phase clock φ. Accordingly, before the first clock φ₁ changesfrom high level to low level, a period appears within which the outputimpedance of the first clock driver 38 exhibits high level (that is, theperiod within which the first PMOS transistor M_(p1) and the first NMOStransistor M_(n1) both exhibit an OFF state). The period is identifiedin FIG. 7 as a "HI" period. Before the second clock φ₂ changes from lowlevel to high level, a period appears within which the output impedanceof the second clock driver 39 exhibits high level (that is, the periodwithin which the second PMOS transistor M_(p2) and the second NMOStransistor M_(n2) both exhibit an OFF state). This period is alsoidentified as a "HI" period in FIG. 7.

Thereafter, the single-phase clock φ changes to high level at time t₂,the two input signals to the first NAND gate 32 (that is, thesingle-phase clock φ and the output signal of the second delay circuit37) are both at low level, and consequently, the output signal of thefirst NAND gate 32 exhibits high level and the first PMOS transistorM_(p1) is OFF. Meanwhile, since the two input signals to the second NORgate 35 (that is, the inverted clock signal φ' and the output signal ofthe first delay circuit 36) are both at high level, the output signal ofthe second NOR gate 35 presents low level, and the second NMOStransistor M_(p2) is OFF. Thereafter, when the single-phase clock φchanges from low level to high level at time t₂, the output signal ofthe first NOR gate 33 changes to low level, and the first NMOStransistor M_(n1) is consequently turned OFF. At this point in time, theinverted clock φ' outputted from the inverter 31 changes to low level,and consequently, the output signal of the second NAND gate 34 changesto high level, and the second PMOS transistor M_(p2) is turned OFF.Since the output signal of the second NAND gate 34 is inputted to thefirst NAND gate 32 by way of the second delay circuit 37, the outputsignal of the first NAND gate 32 changes from low level to high levelafter the delay of the second delay time dt₂ that commences when theoutput signal of the second NAND gate 34 changes to high level. As aresult, the first NMOS transistor M_(p1) is turned ON, and the firstclock φ ₁ changes from low level to high level. Meanwhile, since theoutput signal of the first NAND gate 32 is inputted to the second NORgate 35 by way of the first delay circuit 36, the output signal of thesecond NOR gate 35 changes from high level to low level after the delayof the first delay time dt₁ beginning when the output signal of thefirst NAND gate 32 changes to low level. As a result, the second NMOStransistor M_(n2) is turned ON, and the second clock φ₂ changes fromhigh level to low level. In this manner, in the two-phase clockgeneration circuit 30, the first NMOS transistor M_(n1) and the secondPMOS transistor M_(p2) are turned OFF in synchronism with the risingedge of the single-phase clock φ, and after a delay approximately equalto the second delay time dt₂ from the rising edge of the single clock φ,the first PMOS transistor M_(p1) is turned ON, following which thesecond NMOS transistor M_(p2) is turned ON after a delay timeapproximately equal to the sum dt₁ +dt₂ of the first delay time dt₁ andthe second delay time dt₂ from the rising edge of the single-phase clockφ. Accordingly, before the first clock φ₁ changes from low level to highlevel, a period within which the output impedance of the first clockdriver 38 exhibits high level appears (that is, the period within whichthe first PMOS transistor M_(p1) and the first NMOS transistor M_(n1)are both off). This period is identified as a "HI" period in FIG. 7.Before the second clock φ₂ changes from high level to low level, aperiod within which the output impedance of the second clock driver 39exhibits high level appears (that is, the period within which the secondPMOS transistor M_(p2) and the second NMOS transistor M_(n2) are bothoff). This period is shown as another "HI" period in FIG. 7.

Thereafter, operations similar to the above-described operations fromtime t₁ to time t₂ take place repetitively. Accordingly, in thetwo-phase clock generation circuit 30, the first clock φ₁ and the secondclock φ₂ do not present an overlapping condition of high level andrepeat their level variations in synchronism with the single-phase clockφ. In other words, the first clock φ₁ and the second clock φ₂ maketwo-phase clocks of active high level. In the two-phase clock generationcircuit 30, periods within which the output impedance of the first clockdriver 38 exhibit high level can be produced after the rising edge andafter the falling edge of the single-phase clock φ by individually andindependently controlling at different timings the ON/OFF states of thefirst PMOS transistor M_(p1) and the first NMOS transistor M_(n1) thatconstitute the first clock driver 38, and other periods within which theoutput impedance of the second clock driver 39 exhibit high level can beproduced after the rising edge and after the falling edge of thesingle-phase clock φ by individually and independently controlling atdifferent timings the ON/OFF states of the second PMOS transistor M_(p2)and the second NMOS transistor M_(n2), which constitute the second clockdriver 39. Consequently, through-current which may otherwise be producedupon switching of the first clock driver 38 and the second clock driver39 can be eliminated.

A four-phase clock generation circuit 50 according to the thirdembodiment of a polyphase clock generation circuit of the presentinvention includes, as shown in FIG. 8, an inputting section 60, a firstoutputting section 70₁, a second outputting section 70₂, a thirdoutputting section 70₃, and a fourth outputting section 70₄. Theinputting section 60 includes a first frequency dividing circuit 61₁ fordoubling a frequency of a single-phase clock φ, a second frequencydividing circuit 61₂ for doubling a frequency of a carrier signal C₀ ofthe first frequency dividing circuit 61₁, a first AND gate 62₁ foroutputting an output signal S₁ of high level when both the output signalD₁ of the first frequency dividing circuit 61₁ and the output signal D₂of the second frequency dividing circuit 61₂ exhibit high level, asecond AND gate 62₂ for outputting an output signal S₂ of high levelwhen the output signal D₁ of the first frequency dividing circuit 61₁exhibits low level and the output signal D₂ of the second frequencydividing circuit 61₂ exhibits high level, a third AND gate 62₃ foroutputting an output signal S₃ of high level when the output signal D₁of the first frequency dividing circuit 61₁ exhibits high level and theoutput signal D₂ of the second frequency driving circuit 61₂ exhibitslow level, and a fourth AND gate 62₄ for outputting an output signal S₄of high level when both the output signal D₁ of the first frequencydividing circuit 61₁ and the output signal D₂ of the second frequencydividing circuit 61₂ exhibit low level. The first outputting section 70₁includes a first NAND gate 71₁, a fifth AND gate 72₁, a first NOR gate73₁, a first delay circuit 74₁ to which the output signal of the firstNOR gate 73₁ is inputted, and a first clock driver 75₁ formed from afirst PMOS transistor M_(p1) and a first NMOS transistor M_(n1). Theoutput signal of the first NAND gate 71₁ is inputted to the gate of thefirst PMOS transistor M_(p1), and the source of the first PMOStransistor M_(p1) is connected to a power source voltage terminal 78.The output signal of the first NOR gate 73₁ is inputted to the gate ofthe first NMOS transistor M_(n1), and the source of the first NMOStransistor M_(n1) is grounded. The drain of the first NMOS transistorM_(n1) is connected to the drain of the first PMOS transistor M_(p1),and a first clock φ₁ is outputted from the junction between them. Thesecond outputting section 70₂, the third outputting section 70₃, and thefourth outputting section 70₄ are each constructed similarly to thefirst outputting section 70₁. The first NAND gate 71₁ of the firstoutputting section 70₁ negates the logical AND among the output signalS₁ of the first AND circuit 62₁, the output signal of the second delaycircuit 74₂ of the second outputting section 70₂, the output signal ofthe third delay circuit 74₃ of the third outputting section 70₃, and theoutput signal of the fourth delay circuit 74₄ of the fourth outputtingsection 70₄. The fifth AND gate 72₁ of the first outputting section 70₁logically ANDs the output signal of the second delay circuit 74₂ of thesecond outputting section 70₂, the output signal of the third delaycircuit 74₃ of the third outputting section 70₃, and the output signalof the fourth delay circuit 74₄ of the fourth outputting section 70₄.The first NOR gate 73₁ of the first outputting section 70₁ negates thelogical OR between the output signal S₁ of the first AND circuit 62₁ andthe output signal of the fifth AND gate 72₁. The second NAND gate 71₂ ofthe second outputting section 70₂ negates the logical AND among theoutput signal S₂ of the second AND gate 62₂, the output signal of thefirst delay circuit 74₁ of the first outputting section 70₁, the outputsignal of the third delay circuit 74₃ of the third outputting section70₃ and the output signal of the fourth delay circuit 74₄ of the fourthoutputting section 70₄. The sixth AND gate 72₂ of the second outputtingsection 70₂ logically ANDs the output signal of the first delay circuit74₁ of the first outputting section 70₁, the output signal of the thirddelay circuit 74₃ of the third outputting section 70₃ and the outputsignal of the fourth delay circuit 74₄ of the fourth outputting section70₄. The second NOR gate 73₂ of the second outputting section 70₂negates the logical OR between the output signal S₂ of the second ANDgate 62₂ and the output signal of the sixth AND gate 72₂. The third NANDgate 71₃ of the third outputting section 70₃ negates the logical ANDamong the output signal S₃ of the third AND gate 62₃, the output signalof the first delay circuit 74₁ of the first outputting section 70₁, theoutput signal of the second delay circuit 74₂ of the second outputtingsection 70₂ and the output signal of the fourth delay circuit 74₄ of thefourth outputting section 70₄. The seventh AND gate 72₃ of the thirdoutputting section 70₃ logically ANDs the output signal of the firstdelay circuit 74₁ of the first outputting section 70₁, the output signalof the second delay circuit 74₂ of the second outputting section 70₂,and the output signal of the fourth delay circuit 74₄ of the fourthoutputting section 70₄. The third NOR gate 73₃ of the third outputtingsection 70₃ negates the logical AND between the output signal S₃ of thethird AND gate 62₃ and the output signal of the seventh AND gate 72₃.The fourth NAND gate 71₄ of the fourth outputting section 70₄ negatesthe logical AND among the output signal S₄ of the fourth AND gate 62₄,the output signal of the first delay circuit 74₁ of the first outputtingsection 70₁, the output signal of the second delay circuit 74₂ of thesecond outputting section 70₂ and the output signal of the third delaycircuit 74₃ of the third outputting section 70₃. The eighth AND gate 72₄of the fourth outputting section 70₄ logically ANDs the output signal ofthe first delay circuit 74₁ of the first outputting section 70₁, theoutput signal of the second delay circuit 74₂ of the second outputtingsection 70₂, and the output signal of the third delay circuit 74₃ of thethird outputting section 70₃. The fourth NOR gate 73₄ of the fourthoutputting section 70₄ negates the logical OR between the output signalS₄ of the fourth AND gate 62₄ and the output signal of the eighth ANDgate 72₄.

The operation of the four-phase clock generation circuit 50 is describedwith reference to the timing chart shown in FIG. 9. The first frequencydividing circuit 61₁ outputs the output signal D₁ synchronized with thefalling edge of the single-phase clock φ and outputs the carrier signalC₀ synchronized with the rising edge of the single-phase clock φ. Thesecond frequency driving circuit 61₂ outputs the output signal D₂synchronized with the falling edge of the carrier signal C₀. The outputsignal D₁ of the first frequency dividing circuit 61₁ changes from lowlevel to high level when the single-phase clock φ falls at time t₁ andthen changes from high level to low level when the single-phase clock φfalls again at time t₃. The output signal D₁ of the first frequencydividing circuit 61₁ repeats the level variation for each two clockpulses of the single-phase clock φ. The carrier signal C₀ of the firstfrequency dividing circuit 61₁ changes from low level to high level whenthe single-phase clock φ rises at time t₂, and then changes from highlevel to low level when the single-phase clock φ falls at time t₃. Thecarrier signal C₀ of the first frequency dividing circuit 61₁ repeatsthe level variation for each two clock pulses of the single-phase clockφ. The output signal D₂ of the second frequency driving circuit 61₂changes from low level to high level when the carrier signal C₀ falls attime t₃ and then changes from low level to high level when the carriersignal C₀ falls again at time t₄. The output signal D₂ of the secondfrequency driving circuit 61₂ repeats the level variation for each twoclock pulses of the carrier signal C₀, that is, for each four clockpulses of the single-phase clock φ. As a result, as the logical ANDsbetween the output signal D₁ of the first frequency dividing circuit 61₁and the output signal D₂ of the second frequency driving circuit 61₂ arecalculated individually by the first to fourth AND gates 62₁ -62₄ asdescribed above, the output signals S₁ -S₄ which have a high-levelperiod equal to one period of the single-phase clock φ and aresuccessively displaced from each other by one clock distance (the periodof one clock pulse) of the single-phase clock φ as shown in FIG. 9 areoutputted.

It is assumed that at time t₀ shown in FIG. 9, first to third clocks φ₁-φ₃ all exhibit low level while the fourth clock φ₄ exhibits high level.When the single-phase clock φ falls at time t₁, the output signal D₁ ofthe first frequency dividing circuit 61₁ changes from low level to highlevel, whereby the output signal S₃ of the third AND gate 62₃ changesfrom low level to high level and the output signal S₄ of the fourth ANDgate 62₄ changes from high level to low level. Nevertheless, the outputsignal S₁ of the first AND circuit 62₁ and the output signal S₂ of thesecond AND gate 62₂ remain at low level. As a result, when the outputsignal S₄ of the fourth AND gate 62₄ changes to low level, the outputsignal of the fourth NAND gate 71₄ of the fourth outputting section 70₄changes from low level to high level, and consequently, the fourth PMOStransistor M_(p4) constituting the fourth clock driver 75₄ is turnedOFF. At time t₁, the three input signals to the eighth AND gate 72₄ ofthe fourth outputting section 70₄, that is, the output signal of thefirst delay circuit 74₁, the output signal of the second delay circuit74₂, and the output signal of the third delay circuit 74₃, all exhibithigh level, and consequently, the output signal of the eighth AND gate72₄ exhibits high level. As a result, the output signal of the fourthNOR gate 73₄ exhibits low level, and the fourth NMOS transistor M_(n4)constituting the fourth clock driver 75₄ is OFF. However, when theoutput signal S₃ of the third AND gate 62₃ changes to high level at timet₁, the output signal of the third NOR gate 73₃ of the third outputtingsection 70₃ changes to low level. Since the output signal of the thirdNOR gate 73₃ is inputted to the eighth AND gate 72₄ of the fourthoutputting section 70₄ by way of the third delay circuit 74₃, the outputsignal of the eighth AND gate 72₄ changes to low level after the delaytime dt₃ of the third delay circuit 74₃ from time t₁. Accordingly, attime t₁ +dt₃, the output signal S₄ of the fourth AND gate 62₄ and theoutput signal of the eighth AND gate 72₄, which are the two inputsignals to the fourth NOR gate 73₄, both change to low level, and theoutput signal of the fourth NOR gate 73₄ consequently changes from lowlevel to high level and the fourth NMOS transistor M_(n4) constitutingthe fourth clock driver 75₄ is turned ON. As a result, the fourth clockφ 4 outputted from the fourth clock driver 75₄ changes from high levelto low level. Consequently, with the four-phase clock generation circuit50, a period within which the output impedance of the fourth delaycircuit 74₄ exhibits high level can be assured for the delay time dt₃ ofthe third delay circuit 74₃ immediately before the falling edge of thefourth clock φ₄.

Since the output signal of the fourth delay circuit 74₄ among the threeinput signals to the seventh AND gate 72₃ of the third outputtingsection 70₃ is at low level before time t₁, the output signal of theseventh AND gate 72₃ is at low level. Since the output signal S₃ of thethird AND gate 62₃ is also at low level, the output signal of the thirdNOR gate 73₃ is at high level, and the third NMOS transistor M_(n3)constituting the third clock driver 75₃ is ON. However, when the outputsignal S₃ of the third AND gate 62₃ changes to high level at time t₁,the output signal of the third NOR gate 73₃ changes to low level, andconsequently, the third NMOS transistor M_(n3) constituting the thirdclock driver 75₃ is turned OFF. On the other hand, when the outputsignal S₃ of the third AND gate 62₃ changes to high level at time t₁,only the output signal of the fourth delay circuit 74₄ among the fourinput signals to the third NAND gate 71₃ of the third outputting section70₃ changes to low level. Although the output signal of the fourth NORgate 73₄ of the fourth outputting section 70₄ changes from low level tohigh level at time t₁ +dt₃ as described above, since the output signalof the fourth NOR gate 73₄ is inputted to the third NAND gate 71₃ by wayof the fourth delay circuit 74₄, the four input signals to the thirdNAND gate 71₃ all change to high level after the delay time dt₄ of thefourth delay circuit 74₄ from time t₁ +dt₃. As a result, at time t₁ +dt₃+dt₄, the output signal of the third NAND gate 71₃ changes from highlevel to low level, the third PMOS transistor M_(p3) constituting thethird clock driver 75₃ is turned ON, and the third clock φ₃ outputtedfrom the third clock driver 75₃ changes from low level to high level.Consequently, with the four-phase clock generation circuit 50, a periodwithin which the output impedance of the third delay circuit 74₃exhibits high level can be assured for the delay time of the sum dt₃+dt₄ of the delay time dt₃ of the third delay circuit 74₃ and the delaytime dt₄ of the fourth delay circuit 74₄ immediately before the risingedge of the third clock φ₃.

Similarly, with the four-phase clock generation circuit 50, a periodwithin which the output impedance of the third clock driver 75₃ exhibitshigh level can be assured for the delay time dt₂ of the second delaycircuit 74₂ immediately before the falling edge of the third clock φ₃ asshown by slanting lines in FIG. 9; another period within which theoutput impedance of the second clock driver 75₂ exhibits high level canbe assured for the delay time sum dt₂ +dt₃ of the delay time dt₂ of thesecond delay circuit 74₂ and the delay time dt₃ of the third delaycircuit 74₃ immediately before the rising edge of the second clock φ₂ ;a further period within which the output impedance of the second clockdriver 75₂ exhibits high level can be assured by the delay time dt₁ ofthe first delay circuit 74₁ immediately before the falling edge of thesecond clock φ₂ ; a still further period within which the outputimpedance of the first clock driver 75₁ exhibits high level can beassured for the delay time sum dt₁ +dt₂ of the delay time dt₁ of thefirst delay circuit 74₁ and the delay time dt₂ of the second delaycircuit 74₂ immediately before the rising edge of the first clock φ₁ ; ayet further period within which the output impedance of the first clockdriver 75₁ can be assured by the delay time dt₄ of the fourth delaycircuit 74₄ immediately before the falling edge of the first clock φ₁ ;and a yet further period within which the output impedance of the fourthclock driver 75₄ exhibits high level can be assured by the delay timesum dt₄ +dt₁ of the delay time dt₄ of the fourth delay circuit 74₄ andthe delay time dt₁ of the first delay circuit 74₁ immediately before therising edge of the fourth clock φ₄.

It is to be noted that, while a detailed description is omitted, wherethe frequency dividing circuits of the inputting section are provided bythree stages, an eight-phase clock signal can be generated with asimilar construction to that of the four-phase clock generation circuit50.

A two-phase clock generation circuit 200 according to the fourthembodiment of a polyphase clock generation circuit of the presentinvention is different from the two-phase clock generation circuit 10shown in FIG. 4 in that, as shown in FIG. 10, it includes a delay timesetting section in place of the first delay circuit 16 and the seconddelay circuit 17. Here, the delay time setting section includes first tofourth delay circuits 231₁ -231₄ connected in series to each other,first to fourth transfer gates 232₁ -232₄ interposed between an outputterminal of a first NOR gate 213 and the input terminals of the first tofourth delay circuits 231₁ -231₄, respectively, fifth to eighth delaycircuits 231₅ -231₈ connected in series to each other, fifth to eighthtransfer gates 232₅ -232₈ interposed between an output terminal of asecond NOR gate 215 and the input terminals of the fifth to eighth delaycircuits 231₅ -231₈, respectively, a delay controlling register 23₅ intowhich are stored delay control data constituted from an upper bit D₁ anda lower signal D₂, a first delay controlling inverter 236₁ for invertingthe polarity of the upper bit D₁ of the delay control data outputtedfrom the delay controlling register 235, a second delay controllinginverter 236₂ for inverting the polarity of the lower bit D₂ of thedelay control data outputted from the delay controlling register 235,and first to fourth delay controlling NOR gates 237₁ -237₄. Here, theoutput signal DS₁ of the first delay circuit 231₁ is inputted to asecond NAND gate 214 and a second NOR gate 215. The output signal DS₂ ofthe fifth delay circuit 231₅ is inputted to a first NAND gate 212 andthe first NOR gate 213. Meanwhile, the first delay controlling NOR gate237₁ turns ON the first transfer gate 232₁ and the fifth transfer gate232₅ when both the upper bit D₁ and the lower bit D₂ of the delaycontrol data inputted thereto from the delay controlling register 235exhibit low level. The second delay controlling NOR gate 237₂ turns ONthe second transfer gate 232₂ and the sixth transfer gate 232₆ when theupper bit D₁ of the delay control data inputted thereto from the delaycontrolling register 235 and an inverted signal of the lower bit D₂ ofthe delay control data inputted thereto from the second delaycontrolling inverter 236₂ both exhibit low level. The third delaycontrolling NOR gate 237₃ turns ON the third transfer gate 232₃ and theseventh transfer gate 232₇ when both an inverted signal of the upper bitD₁ of the delay control data inputted thereto from the first delaycontrolling inverter 236₁ and the lower bit D₂ of the delay control datainputted thereto from the delay controlling register 235 exhibit lowlevel. The fourth delay controlling NOR gate 237₄ turns ON the fourthtransfer gate 232₄ and the eighth transfer gate 232₈ when both theinverted signal of the upper bit D₁ of the delay control data inputtedthereto from the first delay controlling inverter 236₁ and the invertedsignal of the lower bit D₂ of the delay control data inputted theretofrom the second delay controlling inverter 236₂ exhibit low level.

The operation of the two-phase clock generation circuit 200 will next bedescribed on the assumption that the delay times of the first to eighthdelay circuits 231₁ -231₈ are all equal to "dt". In the two-phase clockgeneration circuit 200, when delay control data in which upper bit D₁and lower bit D₂ both exhibit low level are stored into the delaycontrolling register 235, only the output signal of the first delaycontrolling NOR gate 237₁ changes to high level, and consequently, thefirst transfer gate 232₁ and the fifth transfer gate 232₅ are turned ON.As a result, the output signal DS₁ of the first delay circuit 231₁inputted to the second NAND gate 214 and the second NOR gate 215 is asignal obtained by delaying the output signal of the first NOR gate 213by the delay time dt since it is provided as the output signal of thefirst NOR gate 213 after passing the first transfer gate 232₁ and thefirst delay circuit 231₁. Meanwhile, the output signal DS₂ of the fifthdelay circuit 231₅ inputted to the first NAND gate 212 and the first NORgate 213 is a signal obtained by delaying the output signal of thesecond NOR gate 215 by the delay time dt since it is provided as theoutput signal of the second NOR gate 215 after passing the fifthtransfer gate 232₅ and the fifth delay circuit 231₅. On the other hand,when delay control data wherein the upper bit D₁ has low level and thelower bit D₂ has high level are stored into the delay controllingregister 235, only the output signal of the second delay controlling NORgate 237₂ changes to high level, and consequently, the second transfergate 232₂ and the sixth transfer gate 232₆ are turned ON. As a result,the output signal DS₁ of the first delay circuit 231₁ inputted to thesecond NAND gate 214 and the second NOR gate 215 is a signal obtained bydelaying the output signal of the first NOR gate 213 by the delay time"2×dt" since it is provided as the output signal of the first NOR gate213 after passing the second transfer gate 232₂, the second delaycircuit 231₂, and the first delay circuit 231₁. In the meantime, theoutput signal DS₂ of the fifth delay circuit 231₅ inputted to the firstNAND gate 212 and the first NOR gate 213 is a signal obtained bydelaying the output signal of the second NOR gate 215 by the delay time"2×dt" since it is provided as the output signal of the second NOR gate215 signal after passing the sixth transfer gate 232₆, the sixth delaycircuit 231₆, and the fifth delay circuit 231₅. Further, when delaycontrol data wherein the upper bit D₁ has high level and the lower bitD₂ has low level are stored into the delay controlling register 235,only the output signal of the third delay controlling NOR gate 237₃changes to high level, and consequently, the third transfer gate 232₃and the seventh transfer gate 232₇ are turned ON. As a result, theoutput signal DS₁ of the first delay circuit 231₁ inputted to the secondNAND gate 214 and the second NOR gate 215 is a signal obtained bydelaying the output signal of the first NOR gate 213 by the delay time"3×dt" since it is provided as the output signal of the first NOR gate213 after passing the "third transfer gate 232₃, the third delay circuit231₃, the second delay circuit 231₂, and the first delay circuit 231₁.On the other hand, the output signal DS₂ of the fifth delay circuit 231₅inputted to the first NAND gate 212 and the first NOR gate 213 is asignal obtained by delaying the output signal of the second NOR gate 215by the delay time "3×dt" since it is provided as the output signal ofthe second NOR gate 215 after passing the seventh transfer gate 232₇,the seventh delay circuit 231₇, the sixth delay circuit 231₆, and thefifth delay circuit 231₅. Meanwhile, when delay control data wherein theupper bit D₁ and the lower bit D₂ both have high level are stored intothe delay controlling register 235, only the output signal of the fourthdelay controlling NOR gate 237₄ changes to high level, and consequently,the fourth transfer gate 232₄ and the eighth transfer gate 232₈ areturned ON. As a result, the output signal DS₁ of the first delay circuit231₁ inputted to the second NAND gate 214 and the second NOR,gate 215 isa signal obtained by delaying the output signal of the first NOR gate213 by the delay time "4×dt" since it is provided as the output signalof the first NOR gate 213 after passing the fourth transfer gate 232₄,the fourth delay circuit 231₄, the third delay circuit 231₃, the seconddelay circuit 231₂, and the first delay circuit 231₁. Meanwhile, theoutput signal DS₂ of the fifth delay circuit 231₅ inputted to the firstNAND gate 212 and the first NOR gate 213 is a signal obtained bydelaying the output signal of the second NOR gate 215 by the delay time"4×dt" since it is provided as the output signal of the second NOR gate215 after passing the eighth delay circuit 231₈, the seventh delaycircuit 231₇, the sixth delay circuit 231₆, and the fifth delay circuit231₅. Accordingly, with the two-phase clock generation circuit 200, thedelay times of the first delay circuit 16 and the second delay circuit17 shown in FIG. 4 can be set to four different delay times. It is to benoted that, by setting the number of bits of the delay control data tobe stored into the delay controlling register 235 to "n" and setting thenumber of stages of two sets of delay circuits to "2^(n) ", "2^(n) "different delay times can be set.

For example, when the voltage is as low as, for example, 3 V (that is,in low-speed operation), the waveforms of rising edges and falling edgesof the first and second clocks φ₁ and φ₂ become deformed as seen fromFIG. 11 due to an influence of the capacitance of several elementsbeginning with first and second drivers 218 and 219. In this instance,if the delay times of the first and second delay times 16 and 17 arefixed as in the two-phase clock generation circuit 10 shown in FIG. 4, aperiod within which the first clock φ₁ and the second clock φ₂ are bothactive (that is, a period within which they are at high level) ispresent, and consequently, where the first and second clocks φ₁ and φ₂are used as latching clocks for latches, for example, of themaster-slave configuration, a malfunction such as direct transmission ofdata occurs. On the other hand, when the voltage is as high as, forexample, 5 V (that is, in high-speed operation), the deformation of thewaveforms of rising and falling edges of the first and second clocks φ₁and φ₂ is limited as shown in FIG. 12. However, if the delay betweenclocks defined by the time from the falling edge of the second clock φ₂to the rising edge of the first clock φ₁ or the time from the fallingedge of the first clock φ₁ to the rising edge of the second clock φ₂ isset to an excessively great value, the period of high level of the firstor second clock φ₁ or φ₂ then becomes excessively short, and therefore,if the first and second clocks φ₁ and φ₂ are used as latching clocks forlatches of, for example, the master-slave configuration, problems suchas failure to latch data may occur. However, with the two-phase clockgeneration circuit 200 shown in FIG. 10, the above-described problem canbe prevented by changing delay control data to be stored into the delaycontrolling register 235 so that, when the voltage is low, the delaybetween clocks may be increased, but when the voltage is high, the delaybetween clocks may be decreased.

It is to be noted that, in the two-phase clock generation circuit 200,while the delay between clocks is set in accordance with delay controldata stored into the delay controlling register 235, the delay betweenclocks can be set otherwise by inputting delay control data from anexternal terminal. Further, as with the four-phase clock generationcircuit 50 shown in FIG. 8, the delay between clocks can be setarbitrarily by making the delay times of the first to fourth delaycircuits 74₁ to 74₄ variable.

While the present invention has been described in conjunction withpreferred embodiments thereof, it will now be possible for one skilledin the art to easily put the present invention into practice in variousother manners.

What is claimed is:
 1. A polyphase clock generation circuit comprising:afirst power source voltage terminal; a second power source voltageterminal; a first clock driver including a P-channel field-effecttransistor with a source connected to the first power source voltageterminal, and an N-channel field-effect transistor with a sourceconnected to the second power source voltage terminal and a drainconnected to a drain of the P-channel field-effect transistor, saidfirst clock driver producing a first clock signal; a second clock driverincluding a P-channel field-effect transistor with a source connected tothe first power source voltage terminal, and an N-channel field-effecttransistor with a source connected to the second power source voltageterminal and a drain connected to a drain of the P-channel field-effecttransistor, said second clock driver producing a second clock signal;and clock driver driving means for turning on the P-channel field-effecttransistor and the N-channel field-effect transistor of said first andsecond clock drivers alternately and independently of each other so thatthe P-channel field-effect transistor and the N-channel field-effecttransistor may not have an ON-state simultaneously with each other, saidclock driver driving means including delay means interconnecting saidfirst and second clock drivers so that the first clock signal and thesecond clock signal do not present an overlapping condition of highlevel.
 2. The polyphase clock generation circuit as claimed in claim 1wherein the second power source voltage terminal is grounded.
 3. Apolyphase clock generation circuit comprising:a first power sourcevoltage terminal; a second power source voltage terminal; invertingmeans for inverting a polarity of a single-phase clock to produce aninverted clock; first logical AND means; first logical OR means; secondlogical AND means; second logical OR means; a first clock driverincluding a first P-channel field-effect transistor with a gate to whichthe output signal of the first logical AND means is inputted and asource connected to the first power source voltage terminal, and a firstN-channel field-effect transistor with a gate to which the output signalof the first logical OR means is inputted, a source connected to thesecond power source voltage terminal, and a drain connected to a drainof the first P-channel field-effect transistor; a second clock driverincluding a second P-channel field-effect transistor with a gate towhich the output signal of the second logical AND means is inputted anda source connected to the first power source voltage terminal, and asecond N-channel field-effect transistor with a gate to which the outputsignal of the second logical OR means is inputted, a source connected tothe second power source voltage terminal, and a drain connected to adrain of the second P-channel field-effect transistor; first delay meansfor delaying the output signal of the first logical OR means by apredetermined first delay time; and second delay means for delaying theoutput signal of the second logical OR means by a predetermined seconddelay time; the single-phase clock and the output signal of the seconddelay means being inputted to the first logical AND means and the firstlogical OR means; and the inverted clock outputted from the invertingmeans and the output signal of the first delay means being inputted tothe second logical AND means and the second logical OR means.
 4. Thepolyphase clock generation circuit as claimed in claim 3 wherein thesecond power source voltage terminal is grounded.
 5. A polyphase clockgeneration circuit comprising:a first power source voltage terminal; asecond power source voltage terminal; inverting means for inverting apolarity of a single-phase clock to produce an inverted clock; firstlogical AND means; first logical OR means; second logical AND means;second logical OR means; a first clock driver including a firstP-channel field-effect transistor with a gate to which the output signalof the first logical AND means is inputted and a source connected to thefirst power source voltage terminal, and a first N-channel field-effecttransistor with a gate to which the output signal of the first logicalOR means is inputted, a source connected to the second power sourcevoltage terminal, and a drain connected to a drain of the firstP-channel field-effect transistor; a second clock driver including asecond P-channel field-effect transistor with a gate to which the outputsignal of the second logical AND means is inputted and a sourceconnected to the first power source voltage terminal, and a secondN-channel field-effect transistor with a gate to which the output signalof the second logical OR means is inputted, a source connected to thesecond power source voltage terminal, and a drain connected to a drainof the second P-channel field-effect transistor; first delay means fordelaying the output signal of the first logical AND means by apredetermined first delay time; and second delay means for delaying theoutput signal of the second logical AND means by a predetermined seconddelay time; the single-phase clock and the output signal of the seconddelay means being inputted to the first logical AND means and the firstlogical OR means; and the inverted clock outputted from the invertingmeans and the output signal of the first delay means being inputted tothe second logical AND means and the second logical OR means.
 6. Thepolyphase clock generation circuit as claimed in claim 5 wherein thesecond power source voltage terminal is grounded.
 7. A polyphase clockgeneration circuit comprising:a first power source voltage terminal; asecond power source voltage terminal; inverting means for inverting apolarity of a single-phase clock to produce an inverted clock; firstlogical AND means; first logical OR means; second logical AND means;second logical OR means; a first clock driver including a firstP-channel field-effect transistor with a gate to which the output signalof the first logical AND means is inputted and a source connected to thefirst power source voltage terminal, and a first N-channel field-effecttransistor with a gate to which the output signal of the first logicalOR means is inputted, a source connected to the second power sourcevoltage terminal, and a drain connected to a drain of the firstP-channel field-effect transistor; a second clock driver including asecond P-channel field-effect transistor with a gate to which the outputsignal of the second logical AND means is inputted and a sourceconnected to the first power source voltage terminal, and a secondN-channel field-effect transistor with a gate to which the output signalof the second logical OR means is inputted, a source connected to thesecond power source voltage terminal, and a drain connected to a drainof the second P-channel field-effect transistor; first variable delaymeans for delaying the output signal of the first logical OR means by afirst delay time; and second variable delay means for delaying theoutput signal of the second logical OR means by a second delay time; thesingle-phase clock and the output signal of the second variable delaymeans being inputted to the first logical AND means and the firstlogical OR means; and the inverted clock outputted from the invertingmeans and the output signal of the first variable delay means beinginputted to the second logical AND means and the second logical ORmeans.
 8. The polyphase clock generation circuit as claimed in claim 7wherein the second power source voltage terminal is grounded.
 9. Thepolyphase clock generation circuit as claimed in claim 7 furthercomprising delay time setting means for setting the first delay time ofthe first variable delay means and the second delay time of the secondvariable delay means.
 10. The polyphase clock generation circuit asclaimed in claim 9 wherein the second power source voltage terminal isgrounded.
 11. A polyphase clock generation circuit comprising:a firstpower source voltage terminal; a second power source voltage terminal;inverting means for inverting a polarity of a single-phase clock toproduce an inverted clock; first logical AND means; first logical ORmeans; second logical AND means; second logical OR means; a first clockdriver including a first P-channel field-effect transistor with a gateto which the output signal of the first logical AND means is inputtedand a source connected to the first power source voltage terminal, and afirst N-channel field-effect transistor with a gate to which the outputsignal of the first logical OR means is inputted, a source connected tothe second power source voltage terminal, and a drain connected to adrain of the first P-channel field-effect transistor; a second clockdriver including a second P-channel field-effect transistor with a gateto which the output signal of the second logical AND means is inputtedand a source connected to the first power source voltage terminal, and asecond N-channel field-effect transistor with a gate to which the outputsignal of the second logical OR means is inputted, a source connected tothe second power source voltage terminal, and a drain connected to thedrain of the second P-channel field-effect transistor; first variabledelay means for delaying the output signal of the first logical ANDmeans by a first delay time; and second variable delay means fordelaying the output signal of the second logical AND means by a seconddelay time; the single-phase clock and the output signal of the secondvariable delay means being inputted to the first logical AND means andthe first logical OR means; and the inverted clock outputted from theinverting means and the output signal of the first variable delay meansbeing inputted to the second logical AND means and the second logical ORmeans.
 12. The polyphase clock generation circuit as claimed in claim 11wherein the second power source voltage terminal is grounded.
 13. Thepolyphase clock generation circuit as claimed in claim 11, furthercomprising delay time setting means for setting the first delay time ofthe first variable delay means and the second delay time of the secondvariable delay means.
 14. The polyphase clock generation circuit asclaimed in claim 13 wherein the second power source voltage terminal isgrounded.
 15. A polyphase clock generation circuit comprising:a firstpower source voltage terminal; a second power source voltage terminal;frequency dividing means for dividing a frequency of a single-phaseclock to produce a plurality of divided frequency signals; and aplurality of outputting means each including first logical AND means,second logical AND means, logical OR means, delay means for delaying theoutput signal of the logical OR means by a predetermined delay time, anda clock driver having a P-channel field-effect transistor with a gate towhich the output signal of the first logical AND means is inputted and asource connected to the first power source voltage terminal, and havingan N-channel field-effect transistor with a gate to which the outputsignal of the logical OR means is inputted, a source connected to thesecond power source voltage terminal, and a drain connected to a drainof the P-channel field-effect transistor; the frequency dividing meansproducing the plurality of divided frequency signals so that any of theplurality of divided frequency signals has a period of high level whichdoes not overlap with a period of high level of any of the other dividedfrequency signals; one of the plurality of divided frequency signalsgenerated by the frequency dividing means and the output signals of thedelay means which constitute the plurality of outputting means exceptfor one of the plurality of outputting means being inputted to the firstlogical AND means which constitutes the one of the plurality ofoutputting means; the output signals of the delay means which constitutethe plurality of outputting means except for the one of the plurality ofoutputting means being inputted to the second logical AND means whichconstitutes the one of the plurality of outputting means; and the one ofthe plurality of divided frequency signals generated by the frequencydividing means and the output signal of the second logical AND meansbeing inputted to the logical OR means which constitutes the one of theplurality of outputting means.
 16. The polyphase clock generationcircuit as claimed in claim 15 wherein the second power source voltageterminal is grounded.
 17. A polyphase clock generation circuitcomprising:a first power source voltage terminal; a second power sourcevoltage terminal; frequency dividing means for dividing a frequency of asingle-phase clock to produce a plurality of divided frequency signals;and a plurality of outputting means each including first logical ANDmeans, second logical AND means, logical OR means, variable delay meansfor delaying the output signal of the logical OR means, and a clockdriver having a P-channel field-effect transistor with a gate to whichthe output signal of the first logical AND means is inputted and asource connected to the first power source voltage terminal and havingan N-channel field-effect transistor with a gate to which the outputsignal of the logical OR means is inputted, a source connected to thesecond power source voltage terminal, and a drain connected to a drainof the P-channel field-effect transistor; the frequency dividing meansproducing the plurality of divided frequency signals so that any of theplurality of divided frequency signals has a period of high level whichdoes not overlap with a period of high level of any of the other dividedfrequency signals; one of the plurality of divided frequency signalsgenerated by the frequency dividing means and the output signals of thevariable delay means which constitute the plurality of outputting meansexcept for one of the plurality of outputting means being inputted tothe first logical AND means which constitutes the one of the pluralityof outputting means; the output signals of the variable delay meanswhich constitute the plurality of outputting means except for the one ofthe plurality of outputting means being inputted to the second logicalAND means which constitutes the one of the plurality of outputtingmeans; and the one of the plurality of divided frequency signalsgenerated by the frequency dividing means and the output signal of thesecond logical AND means being inputted to the logical OR means whichconstitutes the one of the plurality of outputting means.
 18. Thepolyphase clock generation circuit as claimed in claim 17 wherein thesecond power source voltage terminal is grounded.
 19. The polyphaseclock generation circuit as claimed in claim 17 further comprising delaytime setting means for setting delay times of the variable delay meanswhich constitute the plurality of outputting means.
 20. The polyphaseclock generation circuit as claimed in claim 19 wherein the second powersource voltage terminal is grounded.